The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs.
For example, body biasing has been used in traditional process nodes for modulating gate threshold voltage of a transistor. However, body biasing effect has diminished with transistor scaling down. Particularly, in fin field effect transistors (FinFETs), there has not been an effective way of adding body biasing due to geometric limitations. A FinFET typically includes a narrow and tall silicon wall (the “fin”) over a substrate, and further includes a gate engaging the fin on two or three sides thereof. The FinFET's conductive channel is formed on surfaces of the fin adjacent to the gate. Any biasing added to the substrate is unlikely to have any effect on the FinFET's gate threshold voltage and the so-called “body effect” is virtually absent in the FinFET. Accordingly, what is needed is a way of adding effective body biasing to a FinFET.